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| PD - 9.1333B PRELIMINARY Logic-Level Gate Drive Ultra Low On-Resistance Surface Mount (IRLR3103) Straight Lead (IRLU3103) Advanced Process Technology Fast Switching Fully Avalanche Rated IRLR/U3103 HEXFET(R) Power MOSFET D l l l l l l l VDSS = 30V G S RDS(on) = 0.019 ID = 46A Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. D -P A K T O -2 52 A A I-P A K TO -2 5 1 A A Absolute Maximum Ratings Parameter ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ T STG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. 46 29 220 69 0.56 16 240 34 6.9 2.0 -55 to + 150 300 (1.6mm from case) Units A W W/C V mJ A mJ V/ns C Thermal Resistance Parameter Min. Typ. Max. 1.8 50 110 Units C/W RJC Junction-to-Case ---- ---- RJA Junction-to-Ambient (PCB mount)** ---- ---- RJA Junction-to-Ambient ---- ---- ** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994 8/7/96 IRLR/U3103 Electrical Characteristics @ TJ = 25C (unless otherwise specified) V(BR)DSS V(BR)DSS/TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time RDS(on) VGS(th) gfs IDSS I GSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Max. Units Conditions --- V VGS = 0V, I D = 250A --- V/C Reference to 25C, I D = 1mA 0.019 VGS = 10V, ID = 28A 0.024 VGS = 4.5V, I D = 23A --- V VDS = VGS , ID = 250A --- S VDS = 25V, I D = 34A 25 VDS = 30V, VGS = 0V A 250 VDS = 24V, VGS = 0V, TJ = 125C 100 V GS = 16V nA -100 VGS = -16V 50 ID = 34A 14 nC VDS = 24V 28 V GS = 4.5V, See Fig. 6 and 13 --- VDD = 15V --- I D = 34A ns --- RG = 3.4, VGS = 4.5V --- RD = 0.43, See Fig. 10 Between lead, --- 4.5 --- 6mm (0.25in.) nH from package --- 7.5 --- and center of die contact --- 1600 --- VGS = 0V --- 640 --- pF VDS = 25V --- 320 --- = 1.0MHz, See Fig. 5 Min. Typ. Max. Units Conditions MOSFET symbol --- --- 46 showing the A G integral reverse --- --- 220 p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 28A, VGS = 0V --- 81 120 ns TJ = 25C, IF = 34A --- 210 310 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Min. 30 --- --- --- 1.0 23 --- --- --- --- --- --- --- --- --- --- --- Typ. --- 0.037 --- --- --- --- --- --- --- --- --- --- --- 9.0 210 20 54 D G S Source-Drain Ratings and Characteristics IS ISM D S VSD trr Qrr ton Specification changes Rev. # Parameters Old spec. New spec. Comments Revision Date 1 VGS(th) (Max.) 2.5V No spec. Removed VGS(th) Max. Specification 5/1/96 20 16 Decrease VGS Max. Specification 5/1/96 1 VGS (Max.) Notes: Repetitive rating; pulse width limited by Pulse width 300s; duty cycle 2%. max. junction temperature. ( See fig. 11 ) Caculated continuous current based on maximum allowable junction temperature; VDD = 15V, starting TJ = 25C, L = 300H Package limitation current = 20A. RG = 25, IAS = 34A. (See Figure 12) This is applied for I-PAK, LS of D-PAK is measured between lead and center of I SD 34A, di/dt 140A/s, VDD V(BR)DSS , die contact Uses IRL3103 data and test conditions. TJ 150C IRLR/U3103 1000 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTT OM 2.5V TOP 1000 ID , D ra in -to -S o u rce C u rre n t (A ) 100 ID , D ra in -to -S o u rce C u rre n t (A ) VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP 100 10 10 2.5 V 2.5 V 1 0.1 1 20 s PU LSE W ID TH T J = 2 5C 10 A 1 0.1 1 2 0 s PU L SE W ID TH T J = 1 50 C 10 A 100 100 V D S , Drain-to-Source V oltage (V ) V D S , Drain-to-S ource Voltage (V ) Fig 1. Typical Output Characteristics, T J = 25oC Fig 2. Typical Output Characteristics, T J = 150o C 1000 2.0 R D S (o n ) , D ra in -to -S o u rc e O n R e si sta n ce (N o rm a li ze d ) I D = 46 A I D , D r ain- to-S ourc e C urre nt (A ) 1.5 100 T J = 2 5 C TJ = 1 5 0 C 1.0 10 0.5 1 2.0 3.0 4.0 5.0 V DS = 1 5 V 2 0 s P U L S E W ID T H 6.0 7.0 8.0 9.0 A 0.0 -60 -40 -20 0 20 40 60 80 V G S = 10 V 100 120 140 160 A V G S , G ate-to -S ource V olta ge (V ) T J , Junction T emperature (C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature IRLR/U3103 3200 2800 2400 2000 1600 1200 800 400 0 1 10 100 0 0 10 20 30 V G S , G a te -to -S o u rce V o lta g e (V ) C iss C os s V GS C is s C rs s C os s = = = = 0V , f = 1MH z C gs + C g d , Cds SH OR TED Cgd C ds + C gd 15 I D = 34A V DS = 2 4V V DS = 1 5V 12 C , C a p a c ita n c e (p F ) 9 6 C rs s 3 FO R TEST CIR CU IT SEE FIG UR E 13 40 50 60 70 A A V D S , Drain-to-Source V oltage (V) Q G , T otal Gate C harge (nC ) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000 1000 I S D , R e v e rse D ra in C u rre n t (A ) OPE R ATIO N IN TH IS A RE A LIMITE D BY R D S(o n) I D , D ra in C u rre n t (A ) 10 s 100 100 1 00s TJ = 15 0C T J = 25 C 10 1m s 10m s 10 0.4 0.8 1.2 1.6 2.0 VG S = 0 V 2.4 A 1 1 T C = 25 C T J = 15 0C S ing le Pulse 10 2.8 A 100 V S D , S ource-to-Drain Voltage (V ) V D S , Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area IRLR/U3103 50 VDS L IM IT E D B Y P A C K A G E 40 RD VGS RG I D , D ra in C u rre n t (A m p s) D.U.T. + - VDD 30 4.5V Pulse Width 1 s Duty Factor 0.1 % 20 Fig 10a. Switching Time Test Circuit 10 VDS 90% 0 25 50 75 100 125 A 150 TC , Case Temperature (C ) Fig 9. Maximum Drain Current Vs. Case Temperature 10% VGS td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms 10 Therm al R esp onse (Z thJC ) 1 D = 0.50 0 .2 0 0 .1 0 0 .0 5 PD M 0.1 0 .0 2 0 .0 1 S IN G L E P U L S E (T HE RM A L R E S P O NS E ) N o te s : 1 . D u ty fa c to r D = t t 1 t2 1 /t 2 0.01 0.00001 2. P e a k T J = P DM x Z t h J C + T C A 1 0.0001 0.001 0.01 0.1 t 1 , Rectan gular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case IRLR/U3103 VDS D.U.T. RG + V - DD 4.5 V E A S , S in g le P u ls e A va la n c h e E n e rg y (m J) L 500 TO P 400 B OTTO M ID 15 A 2 1A 34 A IAS tp 0.01 300 200 Fig 12a. Unclamped Inductive Test Circuit 100 V(BR)DSS tp VDD VDS 0 VD D = 1 5V 25 50 75 100 125 A 150 Starting T J , Junction Temperature (C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current IAS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50K QG 12V .2F .3F 4.5 V QGS VG QGD VGS 3mA D.U.T. + V - DS IG ID Charge Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit IRLR/U3103 Peak Diode Recovery dv/dt Test Circuit + Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer + - - + * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test + VDD Driver Gate Drive P.W. Period D= P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 13. For N-Channel HEXFETS IRLR/U3103 Package Outline TO-252AA Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 3 0.51 (.020) MIN. 10.42 (.410) 9.40 (.370) LEA D AS SIG NME NT S 1 - G AT E 2 - DRA IN 3 - S OUR CE 4 - DRA IN 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) -B 1.52 (.060) 1.15 (.045) 3X 1.14 (.045) 2X 0.76 (.030) 2.28 (.090) 4.57 (.180) 0.89 (.035) 0.64 (.025) 0.25 ( .010) M AMB 0.58 (.023) 0.46 (.018) NOT ES: 1 DIME NSIO NING & T OLE RANCING P ER A NSI Y 14.5M, 1982. 2 CO NTRO LLING DIMENS ION : INCH. 3 CO NFO RMS T O JEDE C O UTLINE TO -252AA . 4 DIME NSIO NS S HO W N ARE BEF O RE SO LD ER DIP , SO LDER DIP MA X. +0.16 (.006). Part Marking Information TO-252AA (D-PARK) E XA M PL E : T HIS IS AN IR F R1 20 W IT H AS S EM B LY L OT C OD E 9 U 1P INT ER N AT IO N A L R E CT IF IE R L O GO A IR F R 1 20 9U 1P FIR ST P O RT IO N OF P A RT N U MB E R AS S EM B LY L OT CO D E S E CO N D P O RT ION O F PA R T NU M BE R IRLR/U3103 Package Outline TO-251AA Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 1.52 ( .060) 1.15 ( .045) 1 -B 2.28 (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) 2 3 6.22 ( .245) 5.97 ( .235) 1.27 ( .050) 0.88 ( .035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) LEAD AS SIG NMENT S 1 - G AT E 2 - DRA IN 3 - S OURCE 4 - DRA IN NOT ES : 1 DIME NSIO NING & T OLE RANCING P ER A NSI Y14.5M, 1982. 2 CO NTRO LLIN G DIMENS ION : INCH. 3 CO NFO RMS TO J EDE C O UT LINE TO -252AA . 4 DIME NSIO NS SHOW N A RE BEF O RE SO LDER DIP , SO LDER DIP MA X. +0.16 (.006). 3X 1.14 (.045) 0.76 (.030) 3X 0.89 (.035) 0.64 (.025) M AMB 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 2.28 (.090) 2X 0.25 (.010) Part Marking Information TO-251AA (I-PARK) E XA M P LE : TH IS IS A N IR FU 1 20 W ITH A S SE M B LY L O T C OD E 9 U1 P INT E RN AT ION A L R EC T IFIER LO GO IRF U 12 0 9U AS S E MB L Y L OT C OD E 1P F IRS T P O RT IO N O F P A RT N U M BE R S EC O ND PO R TIO N OF P AR T N U MB E R IRLR/U3103 Tape & Reel Information TO-252AA Dimensions are shown in millimeters (inches) TR TRR TR L 1 6 .3 ( .6 4 1 ) 1 5 .7 ( .6 1 9 ) 16 .3 ( .6 4 1 ) 15 .7 ( .6 1 9 ) 1 2.1 ( .47 6 ) 1 1.9 ( .46 9 ) F E E D D IR E C T IO N 8 .1 ( .3 18 ) 7 .9 ( .3 12 ) FE E D D IR E C TIO N N O TE S : 1 . C O N T R O LL IN G D IM E N S IO N : M ILL IM E TE R . 2 . A L L D IM E N S IO N S A R E S H O W N IN M IL LIM E T E R S ( IN C H E S ). 3 . O U T L IN E C O N F O R M S T O E IA -4 8 1 & E IA -5 41 . 1 3 IN C H 16 m m NO T ES : 1 . O U T LIN E C O N F O R M S T O E IA -4 81 . WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 3-30-4 Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 8/96 |
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